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Altera Corporation 33

MAX 9000 Programmable Logic Device Family Data Sheet

Table 22. MAX 9000 Internal Timing Characteristics Note (1)

Symbol Parameter Conditions Speed Grade Unit

-10 -15 -20

Min Max Min Max Min Max

LAD

Logic array delay 3.5 4.0 4.5 ns

LAC

Logic control array delay 3.5 4.0 4.5 ns

Array clock delay 3.5 4.0 4.5 ns

SEXP

Shared expander delay 3.5 5.0 7.5 ns

PEXP

Parallel expander delay 0.5 1.0 2.0 ns

COMB

Combinatorial delay 0.4 1.0 1.0 ns

PRE

CLR

FTD

FastTrack drive delay 0.5 1.0 2.0 ns

LPA

Low-power adder (5) 10.0 15.0 20.0 ns

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Z Microsystems ZX3 Bedienungsanleitung Seite 33