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Altera Corporation 25

MAX 9000 Programmable Logic Device Family Data Sheet

Figure 11. MAX 9000 JTAG Waveforms

Table13 shows the JTAG timing parameters and values for MAX 9000

devices.

For detailed information on JTAG operation in MAX 9000 devices, refer to

Application Note 39 (IEEE 1149.1 (JTAG) Boundary-Scan Testing in Altera

Devices).

Table 13. JTAG Timing Parameters & Values for MAX 9000 Devices

Symbol Parameter Min Max Unit

JCP

TCK clock period 100 ns

JCH

TCK clock high time 50 ns

JCL

TCK clock low time 50 ns

JPSU

JTAG port setup time 20 ns

JPH

JTAG port hold time 45 ns

JPCO

JTAG port clock to output 25 ns

JPZX

JTAG port high impedance to valid output 25 ns

JPXZ

JTAG port valid output to high impedance 25 ns

JSSU

Capture register setup time 20 ns

JSH

Capture register hold time 45 ns

JSCO

Update register clock to output 25 ns

JSZX

Update register high impedance to valid output 25 ns

JSXZ

Update register valid output to high impedance 25 ns

TDO

TCK

JPZX

JPCO

JPH

JPXZ

JCP

JPSU

JCL

JCH

TDI

TMS

Signal

to Be

Captured

Signal

to Be

Driven

JSZX

JSSU

JSH

JSCO

JSXZ

1 2 ... 20 21 22 23 24 25 26 27 28 29 30 ... 45 46

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